Low-jitter/low-voltage phase-locked loops and current-controlled oscillators (PLL-ICOs) operating in noisy power-supply environments with other digital circuits are increasingly important in integrated circuit (IC) designs. These PLL-ICOs are needed to generate clock frequencies for different functional blocks in an IC, such as general purpose processor/memory clocks, analog to digital and digital to analog converter clocks, audio CODEC clocks, digital signal processing clocks, external interface clocks, etc.
In particular, embedded analog circuits such as PLL-ICOs rely on a wide-band noise-free power-supply (VDD) to meet clock phase-noise and timing-jitter requirements. As IC designs progress towards embedding more analog circuits along with digital processors in the same silicon die, it becomes more difficult in the IC design to include independent low-noise power-supply (VDD) connections for each embedded analog core. Low Drop-Out (LDO) voltage regulators have been traditionally used to meet this requirement. However, designing wide-band power supply rejection ratio (PSRR) LDO voltage regulators, using only on-chip components is a difficult design task and there may be a substantial silicon die area penalty for each additional wide-band PSRR LDO voltage regulator.
Traditionally, on-chip PLL-ICOs use independent power-supply (VDD) bumps to get a clean power supply (VDD) connections. The number of power-supply (VDD) bumps increases as multiple PLLs are integrated into an IC. The number of power-supply (VDD) bumps and silicon die bond pads increases as multiple PLL-ICOs and other embedded analog cores are integrated into an IC. The power-supply (VDD) bumps refer to a solder ball connection between a packaged integrated circuit (packaged IC) and the main application circuit board. By improving the PSRR of individual circuit blocks on the IC, such as any PLL-ICOS, the number of power-supply (VDD) and ground (GND) connections can be minimized, thereby reducing the packaged IC pin count, IC and main application circuit board routing complexity.
There is a need for a low-jitter PLL-ICO with improved power supply rejection ratio (PSRR) for integration with other circuit blocks in an IC design. A substantial improvement in PLL-ICO PSRR allows a high-speed/low-jitter PLL-ICO to share power supply (VDD) connection(s) with other circuit blocks within an IC design; thereby IC die size is reduced, die floor-plan and layout are simplified, IC package and die pin count are lessened, and ultimately IC cost is lowered.